Subject: PPC internal timer synch problems on YDL SMP systems?
From: Masden, Larry R (Larry.Masden@PSS.Boeing.com)
Date: Mon Feb 12 2001 - 15:53:02 MST
I note that the 60 ns internal timers on different CPUs of a Synergy Microsystems PPC dual or quad processor YDL SMP systems are not synchonized. The specifics I've seen are that the cpu 0 timer is about 75 ms ahead of others.
I've heard from someone, that didn't have a specific reference to give me, that this was a general YDL problem (not board specific) and was a known problem in some/all? 2.2 YDL kernels and that the problem is fixed in the 2.4 kernel. I need a quicker fix and am looking for some specific's but havn't found them yet.
Does anyone have a reference to this problem / fix that I could look at?
Following is the code that I use to do the raw read the timer's most significant and least significant words:
/* --------------------------------------------------------------------
* code to read a powerPC's 64 bit, 60 ns internal timer
*
* ppctimel:
*
* 0x1db13d8 7c6c42a6 mfspr r3,TBL
* 0x1db13dc 4e800020 blr
*
* ppctimeu:
*
* 0x1db13e0 7c6d42a6 mfspr r3,TBU
* 0x1db13e4 4e800020 blr
* ------------------------------------------------------------------- */
unsigned int ppctimelsw ( )
{
__asm__(" mfspr 3,268 ");
}
unsigned int ppctimemsw ( )
{
__asm__(" mfspr 3,269 ");
}
Thanks
Larry Masden
Larry.R.Masden@Boeing.com
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